This invention relates to a read only memory (ROM), and more particularly to a mask ROM including depletion-type memory cells.
In general, a mask ROM includes a plurality of memory cells arranged in an array or matrix consisting of intersecting word lines and bit lines. Each of these memory cells can be fabricated as a field-effect transistor (FET) in a small area by using a metal-oxide-silicon (MOS) technique. Data is permanently stored in each cell during fabrication of the ROM.
Cross references in this field are as follows:
U.S. Pat. No. 4,080,718, "Method of Modifying Electrical Characteristics of MOS Devices Using Ion Implantation" issued on Mar. 28, 1978; PA0 Electronics, Mar. 30, 1978, pp. 96-99, "Cell Layout Boots Speed of Low-Power 64-K ROM"; and PA0 "A 100 ns 150 mW 64 K bit ROM", described in 1978 IEEE International Solid State Circuits Conference pp. 152-153, SESSION XII: HIGH DENSITY MEMORIES.
In an example of the prior-art devices, the construction of a ROM is such that the gate of each memory cell is connected to one of the word lines, the drain of each cell is connected to one of the bit lines, and a source of each cell is grounded. At a late stage of fabrication of the ROM, when an order for designing the ROM is received, in other words, when the data to be written into the ROM is determined, desired data is permanently stored in each memory cell in such a way that, when using N-channel transistors as memory cells, the particular cells into which information "1" is to be written are subjected to an ion implantation of P-type impurities. By the ion implantation, impurities of the same conducting type as the semiconductor body are injected into the selected channel regions to modify the threshold voltage of the selected cells to a high level. Thus, information "1" is stored in the selected particular cells.
The above-mentioned prior-art device has the advantage of a higher degree of integration in comparison with devices in which, for storing information "0", for example, areas for forming windows through an insulating layer are required to contact a bit line to a drain. Moreover, since data are written at a late stage of fabrication in accordance with the invention, the time between the determination of the write data and the shipping of the products is relatively short in comparison with well known devices in which, in order to write data, diffusion layers are cut at an early stage of fabrication.
However, the ROM obtained by modifying the threshold voltage of selected cells to a high level, as described above, has the following disadvantages. Since the conduction type of the implanted impurities is the same as that of the semiconductor body, the concentration of the impurities in the channel regions or near the channel regions where the impure ions have been implanted becomes high. This results in an increase in junction capacitances between the source and the semiconductor body and between the drain and the semiconductor body, in each selected memory cell. Therefore, the operating speed of the ROM is lowered, because a long time is required to read out data due to the increased capacitance. Moreover, since the depletion layer is narrowed due to the fact that the impurities are of the same conduction type as the semiconductor body, the breakdown voltages between the source and the semiconductor body and between the drain and the semiconductor body are lowered, and the amplitude of the voltage of each bit line is limited.